1. Field of the Invention
The present invention relates to an input circuit of a memory device, and more particularly to an input circuit for a memory device, which improves a data processing speed by controlling transmission paths for data having passed through a data input buffer in response to an input of a block address.
2. Description of the Prior Art
The data processing speed of a semiconductor memory device is gradually accelerating. Moreover, with the development of a DDR SDRAM capable of accessing two data in one clock, the data processing speed of the memory device accelerates further. In particular, a processing for input data is one of issues important for improving the data processing speed of the memory device.
FIG. 1 is a block diagram showing the data input circuit of a conventional memory device. Specifically, the memory device disclosed in the present specification denotes a DDR SDRAM, a DDR2 SDRAM (next generation memory device), etc.
As shown in FIG. 1, the conventional data input circuit includes data buffers 101 and 102, an input multiplexer 103, data bus writers 105 and 106, block writers 107 and 108, and an input selection signal generation circuit 104 for controlling the operations of the data bus writers 105 and 106.
For convenience of description, FIG. 1 shows only two data buffers 101 and 102. However, when the memory device has a data input/output structure of ×16, the number of the data buffers is 16. Accordingly, it is noted that 14 data buffers exist in addition to the data buffers 101 and 102 shown in FIG. 1.
The basic operation of each element is as follows.
The data buffers 101 and 102 controlled by a control signal Din clk receive corresponding data D0 and D1 respectively, and output data D0_and D_. Herein, the control signal Din clk is a signal (or clock) generated by the number of times of BL/2 after a write command and denotes a signal generated in synchronization with the rising edge of a first DQS signal.
The input multiplexer 103 is a circuit for determining transmission paths of the data D0_1 and D_1. Herein, the reason for determining the transmission paths of the data is because the memory device having the data input/output structure of ×16 type may be used in a data input/output structure of ×8 type as the situation requires.
For instance, when a data pin of the memory device is set to ×16, it is assumed that 16 bit data are applied to the memory device. In such a case, the data D0_1 are sent to the data bus writer 105 along a solid line and the data D1_1 are sent to the data bus writer 106 along a solid line. Other data D2_1 , . . . , D15_1 are sent to data bus writers along solid lines.
In a state in which the data pin of the memory device is set to ×16, if is assumed that 8 bit data are applied to the memory device, 8 used buffers of 16 buffers are necessary and the other 8 buffers are unnecessary.
Meanwhile, even though the data pass through the data buffers 101 and 102, it is necessary to determine the data bus writer, to which the data are to be sent, by the input multiplexer 103. For instance, the data D0_1 having passed through the data buffer 101 are sent to one of the two data bus writers 105 and 106 by the input multiplexer 103. Herein, when data having the number of bits smaller than the predetermined number of bits are applied, the input multiplexer 103 includes a function of determining the transmission paths of the data.
The data bus writers 105 and 106 send the data transmitted from the input multiplexer 103 to global input lines gio0 and gio1. When the memory device operates in ×16 type, the data bus writers send the data transmitted from the input multiplexer to the global input lines. Further, when the memory device operates in ×8 type, it is necessary to maintain the output terminal of a data bus writer, to which data are not inputted, in an initialization state or precharge state.
The block writers 107 and 108 send the data to memory blocks through local input lines lio0 and lio1. Herein, the memory block signifies an area subdivided in a memory bank and the memory bank includes a plurality of memory blocks.
The input selection signal generation circuit 104 receives a 2-clock shifted block column address and a control signal clk Din and outputs signals for controlling the operations of the data bus writers 105 and 106. Herein, the 2-clock shifted block column address is a two-clock delayed signal than an input column address inputted by a write command as shown in FIG. 2. That is, the 2-clock shifted block column address is an address for selecting the specific block of the memory bank. The control signal clk Din is a clock signal generated by the number of times of BL/2 after a two-clock delay after the write command. That is, as shown in FIG. 2, the control signal clk Din is a clock signal generated in synchronization with the rising edge of a clock clk at a time point t3.
FIG. 2 is a waveform view illustrating the operation of the circuit of FIG. 1.
In FIG. 2, the clock clk denotes a clock signal applied to the memory device and the control signal Din clk is a signal for controlling the data buffers 101 and 102. Further, the data D0_2 denotes data outputted from the input multiplexer 103 and the control signal clk Din is a two-clock delayed clock signal after the write command. The 2-clock shifted block column address is a signal two-clock delayed than a column address inputted in synchronization with the same clock as the write command input.
In the operation of the memory device, the input selection signal generation circuit 104 enables the data bus writers 105 and 106 when both the 2-clock shifted block column address and the control signal clk Din are in high level.
However, in the prior art, after the 2-clock shifted block column address has been generated, the control signal clk Din is generated after a predetermined period of time passes. That is, after the 2-clock shifted block column address has been generated, the control signal clk Din is generated with a predetermined time margin. Therefore, in the prior art, the operation time of the data bus writer is delayed by the time margin, so that a data transmission speed slows.